Phase-locked loops are used in many applications, including use in local oscillators of wireless transceivers (i.e., receivers and/or transmitters). In certain applications, such phase-locked loops are implemented with analog circuitry. However, as the operating speeds of digital circuits increase, it is becoming more feasible to implement at least portions of a phase-locked loop for traditionally analog applications using digital building blocks. These phase-locked loops are often referred to as All-Digital Phase Locked Loops (ADPLLs).
In operation an ADPLL may be configured to receive a frequency signal (e.g., FREQ) that is representative of a desired output frequency of the ADPLL. When the ADPLL is locked, the phase, frequency, or both, of an output the ADPLL is locked relative to the frequency signal. In certain wireless transceivers, the frequency signal may be generated by a baseband processor, or the like.
In some applications, the ADPLL may include a digital filter within a feedforward path of the ADPLL. In certain designs the digital filter samples the feedforward path at a fixed sampling rate FREF. However, the fixed sampling rate FREF may not be aligned with the output of the ADPLL. For example, an ADPLL is inherently event driven which includes the detection of zero-crossing at the output of the ADPLL. These zero-crossings vary in time, which results in a non-uniformly sampled system. That is, with the sampling rate FREF out of alignment with the output of the ADPLL, jitter may result. This jitter may directly generate undesirable spurs in the output of the ADPLL.